In general, a system using a processor is divided into a synchronous type and an asynchronous type. The synchronous type drives an entire system with a global clock and the asynchronous type drives a required module only to operate the data.
In particular, since the asynchronous type does not use the global clock, the asynchronous type is regarded as a good alternative capable of solving problems of the synchronous type, such as skew of the global clock, jitter, power consumption of a clock tree, or timing closure, and the like.
Since a pipeline structure is generally in a processor structure an asynchronous type processor with the pipeline structure has been developed in recent years.
As one example of the related art, an asynchronous pipeline which controls the data flow of one stage was disclosed in U.S. Pat. No. 6,925,549.
Individual stages of the asynchronous pipeline according to the one example are divided into a data path and a control path. A control processor in the control path assigns a tag value (i.e., a control tag) of each stage in advance.
A previous stage transmits a data tag through the control path and data through the data path. At this point, the previous stage compares control tag of the previous stage with the data tag of the previous stage, and performs a transmission process driving a latch of the data path when control tag and the data tag of the previous stage coincide with each other. A current stage completes processing and transmits the control tag of the current stage and processing result data to a next stage. At this point, the current stage compares control tag of the current stage with data tag of the current stage and transfers a hand shake protocol request signal to the next stage when the control tag and the data tag coincide with each other. By the way, when the control tag and the data tag do not coincide with each other, the hand shake protocol request signal is not generated, and as a result, a stall phenomenon in which the control tag and the processing result data are not transferred to the next stage occurs. One example of the related art could perform a reoperation sensing the stall situation.
However, in the asynchronous pipeline according to one example, since the number of interfaces of all stages is the same and a command used only at the current stage should be continuously transmitted to subsequent stages by hardware, unnecessary power consumption was generated.
As another example of the related art, a parallel processing processor structure adopting an adaptive pipeline is disclosed in Korea Patent Registration No. 10-0861073.
In the asynchronous pipeline according to another example, the position of a stage of the pipeline is adaptively changed according to a command which is being executed and the type of data transferred between stages may be changed by variation of the number of individual stages or the execution command. Further, the data path of the entire system is divided according to the type of the command to process different commands in parallel without increasing hardware.
However, even in the asynchronous pipeline according to another example, the problem related to the power consumption is not largely improved by a variable stage since the command required only at the previous stage should be transmitted to subsequent stages in order to prevent stall.